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BF1100; BF1100R
Dual-gate MOS-FETs
Rev. 02 -- 13 November 2007 Product data sheet
IMPORTANT NOTICE
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NXP Semiconductors
Product specification
Dual-gate MOS-FETs
FEATURES * Specially designed for use at 9 to 12 V supply voltage * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier up to 1 GHz * Superior cross-modulation performance during AGC. APPLICATIONS * VHF and UHF applications such as television tuners and professional communications equipment. DESCRIPTION Enhancement type field-effect transistor in a plastic microminiature SOT143 or SOT143R package. The transistor consists of an amplifier MOS-FET with source
BF1100; BF1100R
and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling.
PINNING PIN 1 2 3 4 SYMBOL s, b d g2 g1 source drain gate 2 gate 1 DESCRIPTION
handbook, halfpage
d 3
d
handbook, halfpage
4
3
4
g2 g1 1
Top view
g2 g1 2 1
MAM125 - 1
2
MAM124
s,b
Top view
s,b
BF1100 marking code: %MY.
BF1100R marking code: %MZ.
Fig.1 Simplified outline (SOT143) and symbol.
Fig.2 Simplified outline (SOT143R) and symbol.
QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj yfs Cig1-s Crs F drain current total power dissipation operating junction temperature forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure f = 1 MHz f = 800 MHz PARAMETER drain-source voltage CONDITIONS - - - - 24 - - - MIN. - - - - 28 2.2 25 2 TYP. MAX. 14 30 200 150 33 2.6 35 - UNIT V mA mW C mS pF fF dB
Rev. 02 - 13 November 2007
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NXP Semiconductors
Product specification
Dual-gate MOS-FETs
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation BF1100 BF1100R Tstg Tj Note 1. Device mounted on a printed-circuit board. storage temperature operating junction temperature see Fig.3 up to Tamb = 50 C; note 1 up to Tamb = 40 C; note 1 - - -65 - CONDITIONS - - - -
BF1100; BF1100R
MIN.
MAX. 14 30 10 10 200 200 +150 +150 V
UNIT mA mA mA mW mW C C
MLD155
MLD156
handbook, halfpage
250
40 Y fs (mS) 30
Ptot (mW) 200
150 20 BF1100R 100 BF1100
10 50
0 0 50 100 150 200 Tamb ( oC)
0 50 0 50 100 150 T j ( oC)
Fig.4 Fig.3 Power derating curves.
Forward transfer admittance as a function of junction temperature; typical values.
Rev. 02 - 13 November 2007
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NXP Semiconductors
Product specification
Dual-gate MOS-FETs
THERMAL CHARACTERISTICS SYMBOL Rth j-a BF1100 BF1100R Rth j-s thermal resistance from junction to soldering point BF1100 BF1100R Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) PARAMETER gate 1-source breakdown voltage gate 2-source breakdown voltage forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage CONDITIONS VG2-S = VDS = 0; IG1-S = 1 mA VG1-S = VDS = 0; IG2-S = 1 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 9 V; ID = 20 A VG2-S = 4 V; VDS = 12 V; ID = 20 A VG2-S(th) gate 2-source threshold voltage VG1-S = 4 V; VDS = 9 V; ID = 20 A VG1-S = 4 V; VDS = 12 V; ID = 20 A IDSX drain-source current VG2-S = 4 V; VDS = 9 V; RG1 = 180 k; note 1 VG2-S = 4 V; VDS = 12 V; RG1 = 250 k; note 2 IG1-SS IG2-SS Notes 1. RG1 connects gate 1 to VGG = 9 V; see Fig.27. 2. RG1 connects gate 1 to VGG = 12 V; see Fig.27. gate 1 cut-off current gate 2 cut-off current VG2-S = VDS = 0; VG1-S = 12 V VG1-S = VDS = 0; VG2-S = 12 V note 2 Ts = 92 C Ts = 78 C PARAMETER thermal resistance from junction to ambient CONDITIONS note 1
BF1100; BF1100R
VALUE 500 550 290 360
UNIT K/W K/W K/W K/W
MIN. 13.2 13.2 0.5 0.5 0.3 0.3 0.3 0.3 8 8 - -
MAX. 20 20 1.5 1.5 1 1 1.2 1.2 13 13 50 50 V V V V V V V V
UNIT
mA mA nA nA
Rev. 02 - 13 November 2007
4 of 15
NXP Semiconductors
Product specification
Dual-gate MOS-FETs
DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL yfs PARAMETER forward transfer admittance CONDITIONS pulsed; Tj = 25 C VDS = 9 V VDS = 12 V Cig1-s input capacitance at gate 1 f = 1 MHz VDS = 9 V VDS = 12 V Cig2-s input capacitance at gate 2 f = 1 MHz VDS = 9 V VDS = 12 V Cos drain-source capacitance f = 1 MHz VDS = 9 V VDS = 12 V Crs reverse transfer capacitance f = 1 MHz VDS = 9 V VDS = 12 V F noise figure f = 800 MHz; GS = GSopt; BS = BSopt VDS = 9 V VDS = 12 V - - - - - - - - - - 24 24
BF1100; BF1100R
MIN.
TYP. 28 28 2.2 2.2 1.6 1.4 1.4 1.1 25 25 2 2
MAX. 33 33 2.6 2.6 - - 1.8 1.5 35 35 2.8 2.8
UNIT mS mS pF pF pF pF pF pF fF fF dB dB
MLD157
handbook, halfpage gain
0
handbook, halfpage
120
MLD158
reduction (dB) 10
Vunw (dBV) 110
(1) (2)
20 100 30 90 40
50 0 1 2 3 VAGC (V) 4
80
0
10
20
30
40 50 gain reduction (dB)
(1) RG = 250 k to VGG = 12 V f = 50 MHz. Tj = 25 C. (2) RG = 180 k to VGG = 9 V fw = 50 MHz; funw = 60 MHz; Tamb = 25 C.
Fig.6 Fig.5 Gain reduction as a function of the AGC voltage; typical values.
Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.27.
Rev. 02 - 13 November 2007
5 of 15
NXP Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
MLD159
handbook, halfpage
20
handbook, halfpage
20
MLD160
ID (mA) 16
V G1 S = 1.4 V 1.3 V 1.2 V
ID (mA) 16
V G2 S = 4 V 3 V
2.5 V 2V
12
12 1.5 V 8
1.1 V 8 1.0 V 4 0.9 V
4 1V
0 0 4 8 12 V DS (V) 16
0 0 0.4 0.8 1.2 1.6 2.0 V G1 S (V)
VG2-S = 4 V. Tj = 25 C.
VDS = 9 to 12 V. Tj = 25 C.
Fig.7 Output characteristics; typical values.
Fig.8 Transfer characteristics; typical values.
handbook, halfpage
250
MLD161
MLD162
I G1 (A)
handbook, halfpage
40
V G2 S = 4 V
200 3.5 V 150
y fs (mS) 30
V G2 S = 4 V 3.5 V 3V
3V 20
100
2.5 V
50
2V
10
2.5 V
2V 0 0 1 2 V G1 S (V) 3 0 0 10 20 I D (mA) 30
VDS = 9 to 12 V. Tj = 25 C.
VDS = 9 to 12 V. Tj = 25 C.
Fig.9
Gate 1 current as a function of gate 1 voltage; typical values.
Fig.10 Forward transfer admittance as a function of drain current; typical values.
Rev. 02 - 13 November 2007
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NXP Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
handbook, halfpage
16
MLD163
MLD164
handbook, halfpage
20
ID (mA) 12
ID (mA) 15
R G1 = 100 k 147 k 180 k 205 k
8
10
249 k 301 k 402 k 511 k
4
5
0 0 20 40 60 I G1 (A) 80
0 0 4 8 12 V GG = V DS (V) 16
VDS = 9 to 12 V. VG2-S = 4 V. Tj = 25 C.
VG2-S = 4 V. RG1 connected to VGG. Tj = 25 C.
Fig.11 Drain current as a function of gate 1 current; typical values.
Fig.12 Drain current as a function of gate 1 supply voltage (= VGG) and drain supply voltage; typical values; see Fig.27.
handbook, halfpage
12
MLD165
handbook, halfpage
12
MLD166
ID (mA) 8
ID (mA) 8
4
4
0 0 2 4 6 8 10 V GG (V)
0 0 4 8 V GG (V) 12
VDS = 9 V; VG2-S = 4 V. RG1 = 180 k (connected to VGG); Tj = 25 C.
VDS = 12 V; VG2-S = 4 V. RG1 = 250 k (connected to VGG); Tj = 25 C.
Fig.13 Drain current as a function of gate 1 voltage (= VGG); typical values; see Fig.27.
Fig.14 Drain current as a function of gate 1 voltage; (= VGG); typical values; see Fig.27.
Rev. 02 - 13 November 2007
7 of 15
NXP Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
handbook, halfpage
50
MLD167
I G1 (A) 40
handbook, halfpage
50
MLD168
V GG = 9 V 8V 7V
I G1 (A) 40
V GG = 12 V 11 V 10 V
30 6V 20 5V 4V 10
30
9V 8V 7V
20
10
0 0 2 4 V G2 S (V) 6
0 0 2 4 V G2 S (V) 6
VDS = 9 V. RG1 = 180 k (connected to VGG). Tj = 25 C.
VDS = 12 V. RG1 = 250 k (connected to VGG). Tj = 25 C.
Fig.15 Gate 1 current as a function of gate 2 voltage; typical values.
Fig.16 Gate 1 current as a function of gate 2 voltage; typical values.
MLD169
MLD170
handbook, halfpage
16
handbook, halfpage
16
ID (mA) 12 V GG = 9 V 8V 7V 6V 8 5V 4V
ID (mA) 12 V GG = 12 V 11 V 10 V 9V 8V 7V
8
4
4
0 0 2 4 V G2 S (V) 6
0 0 2 4 V G2 S (V) 6
VDS = 9 V. RG1 = 180 k (connected to VGG). Tj = 25 C.
VDS = 12 V. RG1 = 250 k (connected to VGG). Tj = 25 C.
Fig.17 Drain current as a function of the gate 2 voltage; typical values; see Fig.27.
Fig.18 Drain current as a function of the gate 2 voltage; typical values; see Fig.27.
Rev. 02 - 13 November 2007
8 of 15
NXP Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
10 2 handbook, halfpage y is (mS) 10
MLD172
10 3 y rs (S) 10 2
MLD173
10 3
rs (deg) rs
10 2
b is 10
y rs 10
1
g is 10 1 10 1 10 1
102
f (MHz)
10 3
102
f (MHz)
10 3
VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C.
VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C.
Fig.19 Input admittance as a function of frequency; typical values.
Fig.20 Reverse transfer admittance and phase as a function of frequency; typical values.
10 2
MLD174
10 2
MLD175
handbook, halfpage
10
y fs (mS) y fs
fs
(deg)
yos (mS) bos 1
10
fs
10 10 1 gos
1 10
1 102 f (MHz) 10 3
10 2 10
102
f (MHz)
10 3
VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C.
VDS = 9 V; VG2 = 4 V. ID =10 mA; Tamb = 25 C.
Fig.21 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.22 Output admittance as a function of frequency; typical values.
Rev. 02 - 13 November 2007
9 of 15
NXP Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
10 2 handbook, halfpage y is (mS) 10
MLD176
10 3 y rs (S) 10 2
MLD177
10 3
rs (deg) rs
10 2
b is 1 10
y rs 10
g is 10 1 10 1 10 1 102 f (MHz) 10 3
102
f (MHz)
10 3
VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C.
VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C.
Fig.23 Input admittance as a function of frequency; typical values.
Fig.24 Reverse transfer admittance and phase as a function of frequency; typical values.
10 2
MLD178
10 2
MLD179
handbook, halfpage
10
y fs (mS)
y fs
fs
(deg)
yos (mS) 1 bos
10
fs
10
10 1
gos 10 2 10
1 10
1 102 f (MHz) 10 3
102
f (MHz)
10 3
VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C.
VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 C.
Fig.25 Forward transfer admittance and phase as a function of frequency; typical values.
Fig.26 Output admittance as a function of frequency; typical values.
Rev. 02 - 13 November 2007
10 of 15
NXP Semiconductors
Product specification
Dual-gate MOS-FETs
BF1100; BF1100R
handbook, full pagewidth
VAGC R1 10 k
C1 4.7 nF C3 12 pF
C2 R GEN 50 VI R2 50 4.7 nF
DUT RG
L1
450 nH
C4 4.7 nF
RL 50
VGG
V DS
MGC420
For VGG = VDS = 9 V, RG = 180 k. For VGG = VDS = 12 V, RG = 250 k.
Fig.27 Cross-modulation test set-up.
Rev. 02 - 13 November 2007
11 of 15
NXP Semiconductors
Product specification
Dual-gate MOS-FETs
Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2 Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 10 mA s11 MAGNITUDE (ratio) 0.986 0.983 0.974 0.960 0.953 0.933 0.915 0.895 0.880 0.864 0.839 ANGLE (deg) -3.6 -7.4 -14.7 -21.8 -28.7 -35.4 -42.0 -47.9 -53.5 -59.6 -65.0 s21 MAGNITUDE (ratio) 2.528 2.531 2.490 2.446 2.412 2.341 2.283 2.205 2.146 2.087 1.998 ANGLE (deg) 174.4 169.8 159.5 149.8 139.8 130.1 120.4 111.6 102.9 93.4 84.4 s12 MAGNITUDE (ratio) 0.001 0.001 0.002 0.002 0.003 0.003 0.004 0.003 0.003 0.003 0.003
BF1100; BF1100R
s22 ANGLE (deg) 63.7 80.7 81.0 80.3 76.3 76.5 79.0 81.5 90.8 106.6 135.4 MAGNITUDE (ratio) 1.000 1.000 0.996 0.994 0.992 0.987 0.984 0.981 0.978 0.974 0.971 ANGLE (deg) -2.0 -4.2 -8.1 -11.9 -15.7 -19.4 -23.0 -26.7 -30.3 -33.9 -37.6
Noise data: VDS = 9 V; VG2-S = 4 V; ID = 10 mA f (MHz) 800 Fmin (dB) 2.00 opt (ratio) 0.67 (deg) 43.9 rn 0.89
Table 3 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 4
Scattering parameters: VDS = 12 V; VG2-S = 4 V; ID = 10 mA s11 MAGNITUDE (ratio) 0.986 0.984 0.974 0.960 0.953 0.933 0.915 0.894 0.879 0.863 0.838 ANGLE (deg) -3.7 -7.4 -14.6 -21.8 -28.7 -35.3 -41.9 -47.8 -53.5 -59.5 -65.0 s21 MAGNITUDE (ratio) 2.478 2.480 2.440 2.400 2.371 2.306 2.255 2.183 2.131 2.080 1.999 ANGLE (deg) 174.7 170.3 160.6 151.4 141.9 132.7 123.6 115.3 107.2 98.2 89.7 s12 MAGNITUDE (ratio) 0.001 0.001 0.002 0.002 0.003 0.003 0.004 0.004 0.003 0.003 0.003 ANGLE (deg) 72.2 80.9 82.7 79.9 77.7 77.1 77.1 79.3 83.9 95.1 115.8 s22 MAGNITUDE (ratio) 1.000 1.000 0.997 0.996 0.994 0.991 0.989 0.986 0.984 0.982 0.980 ANGLE (deg) -1.6 -3.5 -6.6 -9.7 -12.8 -15.8 -18.7 -21.7 -24.6 -27.5 -30.4
Noise data: VDS = 12 V; VG2-S = 4 V; ID = 10 mA f (MHz) 800 Fmin (dB) 2.00 opt (ratio) 0.66 (deg) 43.3 rn 0.97
Rev. 02 - 13 November 2007
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NXP Semiconductors
Product specification
Dual-gate MOS-FETs
PACKAGE OUTLINES
BF1100; BF1100R
handbook, full pagewidth
0.75 0.60
0.150 0.090 4 0.1 max 10 max
o
3.0 2.8 1.9 3
B A 0.2 M A B
10 max
o
1.4 1.2
2.5 max
1 1.1 max
o
2 0.1 M A B
30 max
0.88
0 0.1 1.7
0.48
0 0.1
MBC845
TOP VIEW
Dimensions in mm.
Fig.28 SOT143.
handbook, full pagewidth
0.40 0.25
0.150 0.090 3 0.1 max 10 max
o
3.0 2.8 1.9 4
B A 0.2 M A
10 max
o
1.4 1.2
2.5 max
2 1.1 max 0.48 0.38 1.7 0.1 M B
1 0.88 0.78
30 max
o
MBC844
TOP VIEW
Dimensions in mm.
Fig.29 SOT143R.
Rev. 02 - 13 November 2007
13 of 15
NXP Semiconductors
BF1100; BF1100R
Dual-gate MOS-FETs
Legal information
Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
Rev. 02 - 13 November 2007
14 of 15
NXP Semiconductors
BF1100; BF1100R
Dual-gate MOS-FETs
Revision history
Revision history Document ID BF1100_N_2 Modifications: BF1100_1 Release date 20071113 Data sheet status Product data sheet Product specification Change notice Supersedes BF1100_1 -
*
Fig. 1 and 2 on page 2; Figure note changed
19950425
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2007 Document identifier: BF1100_N_2

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